STM Publisher Elsevier, Netherlands, has announced the release of Intel Xeon Phi Coprocessor High Performance Programming, a book authored by two Intel evangelists, Jim Jeffers and James Reinders. The book has also been selected for Intel’s Recommended Reading List, an industry resource for the most pertinent technical books for professional developers.
The book is said to benefit software engineers, scientific researchers and high performance and supercomputing developers in need of high-performance computing resources, by providing a guide to exploiting the parallel power of the Intel Xeon Phi coprocessor for high-performance computing. It also presents best practices for portable, high-performance computing and a familiar and proven threaded, scalar-vector programming model.
The resource includes simple but informative code examples that explain the unique aspects of this new highly parallel and high performance computational product. It also covers wide vectors, many cores, many threads and high bandwidth cache/memory architecture.
This announcement coincides with the formal dedication of the Stampede supercomputer at the Texas Advanced Computing Center (TACC) in Austin, TX which is currently ranked number seven on the list of Top 500 supercomputers, with over 6400 Intel Xeon Phi coprocessors. Jeffers and Reinders have committed several hundred books to support TACC’s training efforts for Stampede.
The book, published by Elsevier under the Morgan Kaufmann imprint, is available electronically and in print and can be purchased on the Elsevier Store, as well as on ScienceDirect.
Other books on Intel’s Recommended Reading List published under Elsevier‘s Morgan Kaufmann and Newnes imprints include Programming Massively Parallel Processors by David Kirk and Wen-mei Hwu; Structured Parallel Programming: Patterns for Efficient Computation by Michael McCool, James Reinders and Arch Robison; and Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson.
The others in the list include An Introduction to Parallel Programming by Peter Pacheco; Interconnecting Smart Objects with IP by Jean-Philippe Vasseur and Adam Dunkels; and Embedded Systems Design with Platform FPGAs by Ronald Sass and Andrew Schmidt.
